gnucap:user:netlist_import_and_export:qucs [*]

Import and export: Qucs Verilog schematics

There is work in progress to replace the Qucs file format for more transparency, versatility and data exchange based on .. See https://codeberg.org/qucs/gui/src/branch/develop/ROADMAP for the current status.

A Qucs schematic stores a circuit, and a circuit will be represented as a Verilog “module”.

(* qucs_this=42, qucs_that=17 ... *)
module myschematic( [ports go here] );
[parameters..]
[instances..]
endmodule

In a Verilog schematic, instances are explicitly parameterised, and connections are explicit too. This saves a lot of guesswork down the line, and schematics no longer break across Qucs versions. Qucs has a few “special” components which need additional treatment, as well as “simulation commands” and “plots”.

GND

The GND device with one pin connects a network to global ground. In Qucs it has no label, but we add a unique one. We translate an instance of GND, which may look like

<GND * 1 280 300 0 0 0 0>

to

(* qucs_label="*", qucs_mirrored=0, qucs_rotated=0, S0_x1=280, S0_y1=300 *) GND #() gnd__42 ( n_280_300 );

A Verilog implementation of GND may look like

module GND(x);
ground x;
endmodule

Eqn

TODO